[[mpc8560-notes]]
 
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Table of Contents

Communications Processor

  • RISC microcontroller that resides on a separate bus from the e500 core.
  • Handles lower layer communication tasks and DMA control, while the core handle higher layer activities.
  • e500 core interface
    • Parameters are exchanged through dual-port RAM
    • Commands through command register(used for exceptions and error recovery)
    • Interrupts generated by CP
    • Status and event registers of CP
    • When reading/writing to CPM registers/memories and error occurs, it is reported through CPM error registers
      • CEAR - CPM Error Address Register
      • CEER - CPM Error Event Register
      • CEMR - CPM Error Mask Register

CP Commands

  • Issuing Commands
    • Commands are issued through CPCR - CP Command Register.
    • CPCR[FLG] should be set when issuing a command.
    • On command completion CPCR[FLG] is cleared by CP .
    • Commands can be issued only when CPCR[FLG] is not set.
    • Reset command can be issued when CPCR[FLG] is set.
  • Commands can take upto 200 clocks to execute.
  • On an average commands take 40 clocks.

Internal RAM

  • 64KB of static RAM, split into
    • 32KB of inst RAM to store microcode(add ons) provided by Freescale.
    • 32KB of dual-port RAM - parameters and data structures.
  • Inst. RAM can be accessed by e500 to download microcode.
  • DP RAM
    • Can be accessed by CP/e500/SDMA.
    • Stores parameters for FCC, SCC, MCC, SPI, I2C – called parameter RAM
    • Stores buffer descriptors.
    • Holds data buffers???
    • Temporary storage for moving data between FCC FIFO and external memory.
    • Scratch-pad for user software.

CPM Interrupt Controller

  • Receives interrupt sources from the CPM and external pins.
  • 34 interrupts are concentrated on a single interrupt to the core’s PIC.
  • Each source can be masked individually.
  • Interrupt priorities
    • Flexibility in interrupt priority
      • Relative priorities of FCCs, SCCs and MCCs can be modified.
        • Each of the SCCs can be programmed into a set of priority levels in the priority list.
        • Each of the FCCs and MCCs can be programmed into another set of priority levels in the priority list.
        • In grouped scheme, the priority levels for the SCCs all lie just below that for the FCCs and MCCs.
        • In spread scheme, the priority levels are distributed across the entire range of priority levels.
        • The priorites can be programmed through the SCPRR_H and SCPRR_L interrupt priority registers.
      • One interrupt source can be assigned the highest priority.
        • SICR[HP] can be used to specify one interrupt source as having highest priority.
      • SCPRR_H, SCPRR_L and SICR[HP] can be updated dynamically.
  • When an interrupt is received, the corresponding interrupt pending register (SIPNR_H and SIPNR_L) bit is set. When the interrupt is handled, the bit should be cleared by the interrupt handler. If an event register exists within a sub-block, corresponding to the interrupt, the event register bits should be cleared instead.
  • Masking Interrupt Sources
    • CPM interrupts can be masked using SIMR_H and SIMR_L registers.
    • When a interrupt has multiple interrupting events, the user can individually mask the events by programming a mask register within the block.
  • Interrupt vector that allows the core to locate the ISR is made available to the core through SIVEC.
  • If an SIMR bit is masked at the same time that the corresponding SIPNR bit causes an interrupt request to the core, the error vector is issued??? Thus the user should always include an error vector routine. The error vector cannot be masked.
  • Edge detection mode for the external interrupts can be programmed through SIEXR.

Serial Interface with TSA

Fast Communication Controller

  • A 100MHz CPM clock can support
    • 10/100Mbps Ethernet through MII or RMII
    • 155Mbps ATM segmentation and reassembly through UTOPIA on FCC1 and FFC2 only
    • 45Mbps HDLC/transparent data rates
  • Differs from SCC
    • No DPLL support
    • No HDLC bus
    • No BISYNC, UART, AppleTalk/LocalTalk

Registers

  • General FCC Mode Register (GFMR) among other things selects the protocl to use.
    • Has loopback support and echo support for diagnostics.
  • General FCC Expansion Mode Register (GFEMR))
    • Can be used to specify RMII loopback diagnostic mode.
  • FCC Data Synchronization Register (FDSRx) specifies the pattern used in frame synchronization.
    • For ethernet it should be programmed with 0xD555.
  • Transmit-on-Demand
    • The CP periodically polls the R bit of the next TxBD to see if a new frame has to be sent.
    • The polling occurs every 256 serial transmit clocks.
    • By setting Transmit-on-Demand bit the new frame can be transmitted immediately without waiting for 256 clocks.
    • Gives a high priority to the specified TxBD.
    • It can affect the servicing of other buffers.

FCC Buffer Descriptors

  • The frames to be transmitted and the frames received are stored in buffers.
  • The buffers are referenced by a circular table of buffer descriptors.
  • The base of the buffer descriptor table is passed to the FCC.
  • The size of a buffer descriptor is 8 bytes. It contains
Field Bytes
Status Control 2
Length of the frame 2
Buffer pointer 4

  • The buffers and buffer descriptors can be anywhere in system memory.
  • Transmit process
    • On enabling the transmit side, the CP starts with the first BD in the transmit BD table.
    • When the BD is ready it begins processing the BD.
    • Ready is either found by polling of the TxBD[R] bit periodically or when ToD bit is set.
    • When data from the BD has been placed on the FIFO, the CP moves to the next BD.
    • The CP clears the ready bit. (In continuous mode, the R bit remains set.)
    • When the CP sees the wrap bit TxBD[W] set, it goes back to the beginning of the buffer tables.
  • Receive process
    • On enabling the receive side, the CP starts with the first BD in the receive BD table.
    • When data arrives from the serial line, the CP performs the required protocol processing and moves the data to the buffer pointed to by the first BD.
    • When the buffer gets filled up, frame ends or error occurs the BD is closed and the CP moves on to the next BD.
    • When the CP begins using a buffer it checks for the empty bit of the BD. (This check is made on the prefetched copy of the BD???)
    • If the BD is not empty the CP reports a busy error.
    • The CP clears the empty bit after using up a buffer. (In continuous mode, the E bit remains set.)
    • When the BD sees the W bit set, it moves on to the top of the BD table.
  • In frame based protocols, a frame may reside in more than one buffer.
    • If the buffer containing the rest of frame is not available during transmit, within the required time, and under run error is reported by the CP.
    • If free buffers are not available to store the rest of frame during receive, within the required time, a busy error is rreported.

FCC Parameter RAM

  • Has protocol independent and protocol specific areas.
  • Parameter RAM can be read at any time. Can be written only when Transmit and Receive are disabled.
  • Parameters that have to initialized before the FCC is enabled.
    • Temp memory area for receive
    • Temp memory area for transmit
    • Maximum receive buffer length
    • Receive internal state
      • High 8 bits - function code register
      • Lower 24 bits must be cleared
    • Base address of the receive BD table
    • Transmit internal state
      • High 8 bits - function code register
      • Lower 24 bits must be cleared
    • Base address of the transmit BD table

Interrupts and Interrupt Handling

  • When an event occurs it is reported by setting the corresponding bit in the FCCEx register.
  • If the event is not masked in the FCCMx register, the FCC interrupt is set in interrupt controller’s pending register.
  • If the FCC interrupt is not masked in the interrupt controller and interrupt is raised to core’s PIC.
  • Interrupt handling
    • When an interrupt occurs the FCCE register should be read to determine the cause of the interrupt.
    • Events that are to be handled are cleared in FCCE.
    • If TX or TXE(error) were set, free the buffers corresponding to the BDs??? If the transmit speed is fast, more that one transmit buffer may have been sent by the FCC. So process all BDs till one with R bit set is encountered.
    • If RX or RXB(buffer filled up, but not complete frame) or RXF(complete frame), extract the data. If the receive speed is fast, more than on receive buffer may haveen filled. So process all BDs till one with E bit set is encountered. It must be ensured that there is one free empty buffer always, because the BDs are prefeched???
  • There are initialization, re-initialization, recovery sequences provided by Freescale.
  • FCCs can also be disabled on the fly, procedures for this is also provided by Freescale.

CPM Ethernet Controller

  • The ethernet controller can be connected to PHY using MII(Media Indepenedent Interface) or RMII(Reduced Media Independent Interface).
  • The SDMA channels are used to store every byte received into system memory.
  • The FCS is appended to each frame by the ethernet controller.

Ethernet Channel Frame Transmission

  • When the transmitter is enabled,
 
mpc8560-notes.txt · Last modified: 2005/08/12 06:28 by 220.225.128.84
 
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